Computer systems are becoming increasingly pervasive in our society including everything from small handheld electronic devices, such as personal digital data assistants and cellular phones, to application-specific electronic components, such as set-top boxes and other consumer electronics, to full mobile, desktop, and server systems. However, as systems become smaller in size and in price, the need for efficient memory allocation and system management becomes more important.
Server systems have been traditionally characterized by a significant amount of conventional memory and multiple physical processors in the same system (a multiprocessor system), wherein a physical processor refers to a single processor die or single package. The significant amount of resources available to a server system has lead to extremely inefficient allocation of memory space and wasted execution time.
Typically, there are two types of system management interrupts (SMIs) that may be generated in a system, which include hardware (asynchronous) SMIs, such as a battery being low, or software (synchronous) SMIs, such as an operating system (OS) requesting a processor to change frequency or power levels. Usually, a hardware SMI may be handled by either processor without the knowledge of the other processor's save-state area.
However, a software generated SMI may require all the processors in a multiprocessor system to enter SMI before handling the SMI request, because handling a software SMI may require the ability to access each processor's save-state area. The process of having a plurality of processors enter system management mode before handling a SMI is commonly known as synchronization.
Current multiprocessor systems typically utilize an inefficient timeout method for synchronizing processors. For example, if an SMI is received, each processor may wait a specified amount of time before handling the SMI to ensure each processor has entered system management mode (SMM). As an illustrative example, a processor, in a multiprocessor system, may wait the amount of time it takes to execute the longest instruction before handling the SMI to ensure the other processors have entered SMM. As a result, each processor may have already entered SMI, but the system is sitting idle wasting execution time waiting for the timeout period to expire.
Furthermore, present multiprocessor systems allocate system management memory space inefficiently. Due to current addressing limitations, a typical SMM area may require at least 64 kB. However, not all of this memory space is filled by SMM code and/or data. In addition, each processor is usually assigned separate and distinct 64 kB SMM spaces. Therefore, each 64 kB SMM space has memory space that is not be utilized, but is dedicated to an individual processor.
Nevertheless, these inefficient methods of synchronization and system management memory allocation are not limited to multiprocessor server systems. In fact, these inefficiencies may exist in other systems, such as mobile multiprocessor systems. Hyper-Threading Technology (HT) is a technology from Intel® Corporation of Santa Clara, Calif. that enables execution of threads in parallel using a signal physical processor. HT incorporates two logical processors on one physical processor (the same die). A logical processor is an independent processor visible to the operating system (OS), capable of executing code and maintaining a unique architectural state from other processor in a system. HT is achieved by having multiple architectural states that share one set of execution resources.
Therefore, HT enables one to implement a multi(logical)processor system in a mobile platform. As shown above, inefficient memory allocation and processor synchronization exist in traditional multiprocessor systems, such as server systems. Accordingly, as multiprocessor systems begin to infiltrate the mobile realm, where resources such as memory are limited, the need for optimizations of the aforementioned inefficiencies becomes even more important.